The execution of one instruction.


The Instruction cycle.

Knowing the instruction-cycle can be useful to understand the timing of instructions and the relations between different instructions-codes. On finishing the previous instruction the Static Register (SR) would zeroize itself, that would make the CPU look for the continuation-instruction that according the M/C-flip-flop (MC) was found in the M or the C part of the finished instruction in rC. On an address-match the SR would set in itself bit 1, to become 01 which made the word entering the logic to be sent to register C (rC). MC was then set to M. ( This is why instruction-code (IC) 01 in a program would force the CPU to perform a jump to address 0000. ) Since the instruction in rC was circling around, it was not suited to control functions, therefor the IC was copied to the SR, existing out of 9 flip-flops (2 decimals and a sign), which controlled the logics. If the sign or the 4-bit of SR was high, an adder was made active, this would increment (M) of rC with the contents of an Index-register for comparison it with the timing-band-addresses. Note that in this addition the carry from the 100 bit to 200 was ignored. This was done to simplify the programming of a loop processing data within one band. To decrement the address in M, one had to use the 200- or the 10000-complement. Also an overflow in M was discarded. An (IR) of 0195 had the meaning of minus 5. After this addition both sign and 4 bit in SR were reset. Then the CPU would start to look for a match between the timing-band-addresses and M. On a match again it would set bit 1 of SR. The setting of this bit allowed the data to be read into one of the registers. That is why instruction 26 is the same as instruction 25 with an operand zero. 26 is executed the same way, but no data was read. This applied to all memory-reading-instructions with an M. Some of the instructions were processed in several stages, for each stage SR could set itself to a specific number. There was no hardware-check for misuse of these second- or third-stage instruction codes in programs. When the operand entered the logics, the SR controlled the available functions between entry and the registers. Shifting to the left was done by extending the length of a register with one word-time by one bit (2 ferractors) and shifting to the right was performed by bridging the gap and shortening the register till 11 bits for one word-time. This was performed during the shift-instructions and in multiplying and in dividing. On completion, SR would zeroize itself and the process would start all over. Transferring data from the interlace-patterns to or from the buffers for card-IO was controlled by signals of the timing-band and these transfers happened on one instruction and took one drum-revolution. All IO-actions were performed autonomously by the IO-hardware with the transfers to and from the buffers. Writing or reading the interlace-patterns had to be programmed seperately. Writing the print-interlace-pattern to the buffer would take 3 revolutions, since interface-speed demanded that this data was copied four times onto the print-buffer. Multiplying and division operations could be truncated by placing a sentinel (1/4)in the operand. When the arithmetical logic was about to process such a sentinel, it would terminate the execution. On overflow the reading of C was delayed for one word-time, there was no addition. So an overflow with (C)=0199 would give a continuation in 0000. ---                   
return to menu